DINACON Brief Description
CCD camera system with a two-port controller
(click on this image to see Hi-Res picture)
Here we present a description of the preliminary version of the controller. The information about the final version will be available in July - August 1998.
The CCD controller is designed for control of monolithic CCD arrays, mosaic and IR-detectors and provides:
- best photometric characteristics;
- realization of all basic ways of charge accumulation and readout;
- over-all programmability and flexible automatic adjustment;
- telemetry of control signals, powers, temperature, and self-diagnostics;
- high-degree reliability.
The CCD controller is an intelligent measuring system and when operated in combination with a selected image detector ensures:
- lowest readout noise;
- highest charge measurement accuracy;
- wide range of readout rates.
1. Control of charge accumulation and readout in the CCD detector:
- cleaning of the photosensitive region;
- accumulation of charge under standard or MPP conditions;
- charge readout (frame, drift, fragmental, with binning, or any other program-controlled);
- combined performance (accumulation in the accumulation section and readout by means of the charge transfer section).
2. Program control of the CCD detector and telemetry of:
- timing diagram of control signals;
- amplitudes of control signals;
- electric regimes of output stages of the CCD detector;
- temperature of the CCD detector.
3. Digital processing and correction of the video signal, calibration of the video channel:
- very low - noise preamplifying;
- digital filtering of the video signal at optimum and accelerated readout rates;
- parallel double channel processing to ensure large signal dynamical range;
- digital correction for the bias, the gain and nonlinearity of the readout channel transfer characteristic, including the output MOSFET;
- support of calibration and correction of the charge-to-digital transfer characteristic.
4. Automatic examination of characteristics of the output MOSFET and optimization of its performance:
- obtaining the noise power spectrum as dependent on drain current and voltages;
- determination of the correlation function of the noise process;
- calculation of parameters of the digital filter;
- calculation of parameters of signal correction in real time;
- definition of the optimum regime of the MOSFET.
1. Modular structure
The controller incorporates the following functionally complete modules:
- system controller;
- clock generator with drivers;
- communication adapters.
The system controller provides reception of control commands and data from the host computer, transmission of digital images to it, formation of signals of synchronization of the modules, interaction with other modules, control of the external electromechanical devices.
The generator & drivers forms sequences of clock pulses, controls digitally the amplitude of pulses, enables telemetric control of the pulse amplitude, controls and stabilizes the detector temperature.
The digital videoprocessor provides formation of the video signal and its processing by the matched digital filter at low readout rates and by the double differential averaging at high readout rates, calibration of the the readout channel transfer characteristic, correction of signal amplitude distortions, measurement of the noise power spectrum and control and optimization of the output MOSFET electric regime.
The communication adapters realize connection between the host-computer and the CCD controller through the fast fiber-optics line at a great distance.
The modules are built on the basis of printed circuit boards of 100 x 220 mm2 and housed in a 19 case. In the CCD system the controller is mounted on a cryostat or in close proximity to it.
2. The architecture of the CCD controller
The controller is an open real time system whose architecture is intended to provide flexible detector control and fast accurate processing of signals. The controller has an extensible structure with a high throughput of interprocessor communications.
Processors The main type of the processor is the high-performance digital signal processor ADSP-2106x SHARC (Super Harvard Architecture Computer) to perform tasks of control and multichannel signal processing.
The processor has a throughput rate of 40 MIPS, 25 ns instruction rate, single-cycle instruction execution.
The memory of the processor ADSP-216x includes the internal SRAM 4/2 Mbit and an optional external memory:
- up to 8 MBytes of DRAM in the system controller;
- up to 16 MBytes of SDRAM in the videoprocessor;
- up to 8K x 48 of SRAM in the generator of control signals.
The auxiliary processor is the 16-bit ADSP-2181 designed for synchronization of the CCD controller and control of external electromechanical devices.
Communications Internal interprocessor communications are executed by means of:
- LINK ports with a throughput up to 40 MBytes/s;
- serial ports SPORT with a throughput up to 40 Mbit/s.
External communications of the controller with the host computer are performed through a local PCI-bus and changable PMC adapters:
- IEEE 802.3 (10 Mbit/s) for the low-speed single-port configuration;
- Fibre Channel (266/1062.5 Mbit/s) for the high-speed multiport configuration.
The external electromechanical devices are controlled by RS-232 or SPORT interfaces.
Topology The style of interprocessor connections of the controller is a mixed-type topological structure :
- tree-type structure of connections in the signal processing channel with the total number of processors up to 32;
- linear chain in the control channel with the number of processors up to 32.
The style of multiprocessing is based on the fine-grain homogenous SIMD architecture with hard synchronization of tasks.
In Fig. 1 and 2 are presented the versions of a multiport CCD system with a mosaic-type detector and a single-port system with a single array, respectively.
Fig. 1. The block-diagram of a multiport CCD system
Fig. 2. The block-diagram of a single-port CCD system
Parameter Type Min./ Max. Unit System
System clock frequency 40 MHz Type of interface for videoprocessor LINK Number of videoprocessors 1 / 32 Type of interface for generator/drivers SPORT Number of generator/drivers 1 / 32 Generator &
Number of control clocks formed 44
Range of clock amplitudes -10 / +10 V Resolution of DACs 12 bit Resolution in time domain 25 ns Videoprocessor Number of channels of processing 2 / 4 Number of output stages serviced 2 / 4 Number of bias voltages formed
per CCD output stage
5 Rate of pixel processing:
a) with fast readout
b) with low readout noise
0.5 / 2.5
50 / 500
a) with fast readout
b) with low readout noise
14 / 16
18 / 20
Resolution of ADC 14 bit ADC sampling frequency 10 MHz Intrinsic readout noise:
a) at 500 kHz
b) at 2.5 MHz
Communication adapters Interface type/Controller bus/Host computer bus and rate of data exchange for low-speed version IEEE 802.3/
Interface type/Controller bus/Host computer bus and rate of data exchange for high-speed version Fibre
DINA System for Windows 95/NT
DinaSys for Windows 95/NT is intended for joint operation with the CCD controller DINACON and enables:
- charge accumulation and readout control in a CCD, mosaic detector or IR array;
- display, analysis and storage of large images;
- adjustment of detector regimes;
- telemetric data analysis;
- automatic inspection of the output MOSFET characteristics.
1. CCD system control
- control of detector cleaning, charge accumulation and transfer;
- definition of coordinates of the image subregions being read out with setting the readout speed for each;
- control in the interactive mode or by means of macroses;
- provision of remote networking of the controller.
2. Adjustment, telemetry and diagnostics
- editing timing diagrams of detector control signals;
- set-up and telemetry of the clock levels and biases as well as visual representation of timing diagrams of control signals;
- adjustment and control of the detector temperature;
- manual and automatic adjustment of the detector output stages;
- inspection of the CCD controller, issuing trouble messages;
- testing and diagnostics of communication lines and controller units.
3. Display and storage of images
- gray-level or pseudo-color display with a possibility of modifying the palette and intensity transformation table;
- visual representation of large images optimized for speed;
- zoom, squeeze, pan, scroll, fit in the window or screen;
- writing a rectangular region into a separate file;
- read/write native image files (16 and 32 bit) (DINA file format); read/write FITS image files (16 and 32 bit); write Windows Device Independent Bitmap (8 bit with color palette).
4. Interaction with an image
- reading intensity values of pixels;
- select points, rectangular or ellipse region-of-interest for calculation of statistical characteristics;
- plotting two-dimensional line profiles with the value averaged along X or Y axis;
- writing line profile, histogram and results of calculation into a file;
- switching a magnifier for viewing individual image fragments.
5. Image analysis
- construction of a histogram of intensity distribution in a selected fragment;
- calculation of statistical characteristics (median and mean value, standard deviation, asymmetry and excess coefficients);
- definition of the object centroid, computation of its FWHM, length and angle of the major and minor axes, moments;
- determination of the background value.
6. Determination of the output MOSFET characteristics
- manual or automatic variation of drain current, voltages at the gate and drain and construction of current-voltage characteristics;
- calculation of transconductance over the gate and substrate and differential drain-source conductance and plotting them versus the MOSFET mode;
- measurement of the transfer coefficient nonlinearity as a function of mode;
- measurement of the MOSFET noise spectrum;
- plot of measurement results.
7. Miscellaneous functions
- access to the library of functions of controller operation;
- formation of an observing log for a night;
- editing the FITS header;
- detailed on-line help;
- various tests to derive the controller accuracy characteristics.
Command language DinaLang
The DinaSys-built-in simple and powerful language DinaLang makes it possible to create programmes for control of each adjustment parameter of the CCD controller DINACON, to read of data and to reduce images.
DinaLang includes over 50 commands and provides:
- access to external variables and structural elements;
- writing of complex series of commands into macrofiles;
- addition of macroses determined by the user to the menu Macros.
Minimum system requirements
For the measuring system with a single chip of 1024 x 1024 pixels to be efficient, one needs a host computer incorporating the following:
- Intel 80486 or higher processor.
- 16 MB minimum, RAM of 32MB is recommended. A larger RAM will significantly improve DinaSystems performance and increase the number of images that can be opened.
- 16 MB minimum of free hard disk space.
- Display system capable of 256 colors or more at a resolution of 800x600 pixels or higher. A true-color system is recommended.
- Microsoft Windows 95 or Microsoft Windows NT version 3.51 Operating System or a later one.
Image Storage and Memory Requirements:
Bits per pixel Storage
1024 x 1024 16 2 megabytes 3 megabytes 1024 x 1024 32 4 megabytes 6 megabytes